1. Field of the Invention
The present invention relates to digital telephone transmission, and more particularly, to a system for aligning framing bits from independent digital transmission facilities with framing of a higher transmission rate facility such as SONET.
2. Description of the Prior Art
The American National Standard Institute, Inc. (ANSI) T1.105-1988 describes the Synchronous Optical Network (SONET) protocol for telecommunications equipment. This standard is incorporated herein by reference. The SONET protocol is particularly adapted for optical transmission, and various transmission levels have been standardized at specified line rates in M bit/s. The first level, Optical Carrier Level 1, or OC-1, transmits data at the rate of 51.84 M bits/s. This carrier level has a corresponding electrical level called Synchronous Transport Signal Level 1, or STS-1.
In order to access this high-frequency carrier level, access products are required so that lower bandwidth carriers can the introduced into or extracted from the STS-1 transmission level. These access products provide a SONET network with nodes where components of an STS-1 signal can be added to or dropped out of the main signal. The components that are added to the main signal must be inserted so as to maintain the integrity of the SONET signal. A typical sub-component of an STS-1 SONET signal is a DS1 signal having a bit rate of 1.544 M bit/s. Twenty-eight DS1 signals can be supported by an STS-1 carrier. Within the DS1 signal format twenty-four DS0 64 K bits/s signals can be supported plus one 8K bits/s framing signal.
The SONET transmission is serial, comprising a total of 810 serial bytes. The frame structure for an STS-1 is shown in FIG. 1. The frame comprises 90 columns.times.9 rows of bytes, with 8 bits per byte. The sequence of transmission of the bytes is row by row, from left to right. The frame is divided into three parts: the section and line overhead, which are contained in the first three columns; and the payload, which is found in the 87 remaining columns. The 87 payload columns and the nine rows form a Synchronous Payload Envelope (SPE) which includes 783 bytes. Nine of the SPE bytes are allocated to path overhead.
The SPE can begin anywhere within the 87.times.9 byte envelope. Typically, the SPE begins in one SONET frame and ends in another. A payload pointer provided in overhead bytes H1 and H2 points to the byte where the SPE begins, shown, for example, as P=0 in FIG. 1. The information within the SPE is transported in Sub-STS-1 payloads called Virtual Tributaries, or VTs. There are several levels of VTs; however, it is only necessary to deal with VT 1.5 for purposes of describing this invention. When the STS-1 payload supports 28 DS1 services, one VT at the 1.5 level is provided for each DS1 service.
The 783 bytes of one SPE belong to 28 tributaries, wherein each tributary can carry a DS1 payload. The SONET bytes are mapped into a DS1 payload as illustrated in FIG. 2. The DS1 payload has 27 bytes, 24 of which carry DS0 channels. The first byte carries a VT pointer, or address; a second byte is unused; and the third byte carries signaling data and the framing bit for the DS1 payload. The framing bit of each DS1 has a repetitive pattern that is used by equipment to locate the DS0 channel data, and indicates the DS1 signaling frame. The specific framing pattern for each DS1 can vary and include such features as embedded data channels, but the pattern commonly represents a 12 or 24 channel multiframe.
FIG. 3 illustrates the transmission order of the SONET payload contained within the SPE's of 24 SONET frames. For the sake of clarity, a number of bytes or rows of the SPE are not shown in FIG. 3. These bytes include: the bytes in the first two rows of each SPE, which would contain bytes 1 and 2 of each of the 28 tributaries as shown in FIG. 2, the nine path overhead bytes, and additional `fixed stuff` bytes. In addition, the SPE has been shown as being located entirely within one SONET frame while in most cases the SPE will occupy parts of two SONET frames. Removing these two rows facilitates the illustration in FIG. 3 of the signaling bits provided in each SONET frame. The framing bit is not shown in FIG. 3, but it follows the signaling bits in each byte as shown in FIG. 2. Thus, the first row of each frame shown in FIG. 3 is the signaling and framing row and contains byte number 3 for each of the tributaries. The transmission order proceeds from left to right in each descending row of a frame. Thus, bytes containing four signaling bits and one framing bit for tributaries 0-27 are transmitted in sequence, after which the data for channel 0 of each tributary is transmitted, followed by the data for the other channels through to the transmission of the data for channel 23.
Due to the presence of nine overhead bytes (not shown), bytes 1 and 2 of each tributary, and additional unused `fixed stuff` bytes in the SPE, the signaling bytes start with SPE byte 60 and continue through byte 87.
The SONET format specifies the multiframe pattern shown in FIG. 3 with a path overhead byte, called the H4 multiframe indicator byte carried in the SPE. The H4 multiframe indicator byte applies to every VT in the SPE. In an operative system the framing bit sequence in each VT must be aligned with the H4 multiframe indicator byte of the SPE. The SONET H4 byte is formatted as follows:
______________________________________ Bits - 7 6 5 4 3 2 1 0 Data - P1 P0 SI2 SI1 C3 C2 C1 T ______________________________________
The C3, C2, and C1 bits are unused bits, since they relate to a 2.048M b/s standard which is not used in North America. Thus, the part of the H4 byte of interest consists of five bits and can have values of 0 to 23 to identify any one of 24 consecutive SONET frames transmitted in SPE's. Table 1 illustrates the H4 bytes for frames (FR) 0-23 and the associated SONET formatted signalling for ESF and SF signalling which may be provided in each frame.
Access products that introduce DS1 signalling into the SONET network are required to align with the SONET H4 multiframe indicator byte, when the SONET format is in byte synchronous mode. Potentially, each DS1 signal (up to 28) can have a different alignment from the H4 multiframe indicator byte and from the other twenty-seven DS1 signals being added to the SONET network. There are no known solutions to the problem of aligning DS1 signals with the SONET H4 multiframe indicator byte.
In the access products for which this invention was conceived, a 16-bit internal byte is used for each channel, with each bit being provided on a separate line of a parallel bus. Thus, for each clock pulse a complete 16 bit byte of information is obtained. The internal format for a 16-bit byte is as follows:
__________________________________________________________________________ Bit No: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 D7 D6 D5 D4 D3 D2 D1 D0 A B C D MFS MFS2 P __________________________________________________________________________
The internal 16-bit bus operates at a higher bandwidth and has a total of 32 channels available. One channel is assigned specifically to each of the 24 channels of the DS1 signals. The remaining channels are used for various control functions, specifically, one of the channels is used for the signaling and framing information. The internal 16-bit bus is described in detail in U.S. patent application Ser. No. 351,458 filed May 12, 1989 and entitled "Serial Transport Frame Format Method", said application being commonly assigned herewith and incorporated herein by reference.
The SONET byte which carries the framing bit (F) is formatted as follows:
______________________________________ Bit No. D7 D6 D5 D4 D3 D2 D1 D0 SONET R R S1 S2 S3 S4 F R ______________________________________
In the above, the R bits are not used, the S1-S4 bits are signaling bits as shown in the bytes of FIG. 3, and the F bit is the framing bit.
In the system for which this invention was conceived, the SONET format given above is also used for the bits D7-D0 of the internal 16-bit signaling and framming byte. Of the additional bits in the internal format, MFS and MFS2 bits indicate the multiframe address of the F bits in the VT level 1.5 or DS1 handled by the tributary. Table 1 also shows the relationship between the MFS bit and the SONET H4 bytes in an aligned system.
TABLE 1 __________________________________________________________________________ Signaling Frame Sequence H4 Bytes ESF MFS FR P1 P0 SI2 SI1 T S1 S2 S3 S4 SF __________________________________________________________________________ 1 0 0 0 0 0 0 A0 A1 A2 A3 A bits 1 1 0 0 0 0 1 A4 A5 A6 A7 (same as ESF) 1 2 0 0 0 1 0 A8 A9 A10 A11 1 3 0 0 0 1 1 A12 A13 A14 A15 1 4 0 0 1 0 0 A16 A17 A18 A19 1 5 0 0 1 0 1 A20 A21 A22 A23 1 6 0 1 0 0 0 B0 B1 B2 B3 B bits 1 7 0 1 0 0 1 B4 B5 B6 B7 (same as ESF) 1 8 0 1 0 1 0 B8 B9 B10 B11 1 9 0 1 0 1 1 B12 B13 B14 B15 1 10 0 1 1 0 0 B16 B17 B18 B19 1 11 0 1 1 0 1 B20 B21 B22 B23 0 12 1 0 0 0 0 C0 C1 C2 C3 A bits 0 13 1 0 0 0 1 C4 C5 C6 C7 0 14 1 0 0 1 0 C8 C9 C10 C11 0 15 1 0 0 1 1 C12 C13 C14 C15 0 16 1 0 1 0 0 C16 C17 C18 C19 0 17 1 0 1 0 1 C20 C21 C22 C23 0 18 1 1 0 0 0 D0 D1 D2 D3 B bits 0 19 1 1 0 0 1 D4 D5 D6 D7 0 20 1 1 0 1 0 D8 D9 D10 D11 0 21 1 1 0 1 1 D12 D13 D14 D15 0 22 1 1 1 0 0 D16 D17 D18 D19 0 23 1 1 1 0 1 D20 D21 D22 D23 __________________________________________________________________________
The access products used to extract and add sub-components to the STS-1 transmission level include both an add-drop multiplexer and a terminal multiplexer. The terminal multiplexer receives and extracts all data from the STS-1 and inserts new data in a return path. The add-drop multiplexer, however, poses special problems, since it facilitates the extraction and/or addition of any number of channels carried on the STS-1 line. Thus, some channels pass directly through an add-drop multiplexer, while some channels are extracted and other channels are added.
All received VTs are converted to the internal format. Thus, the through VTs could be treated similarly to the added VTs by realigning them to the H4 multiframe indicator similarly to the added VTs. However, this would cause unnecessary delay for the through VTs, due to processing by the multiplexer. Preferably this delay should be avoided by passing each through tributary directly through the multiplexer and only aligning the tributaries being added.